NAND-based flash memories are widely used as the solid-state memory storage due to their compactness, low power consumption, low cost, high data throughput and reliability. Solid state drive (SSD) devices commonly employ NAND-based flash memory chips and a flash controller to manage the flash memory and to transfer data between the flash memory and a host computer.
An issue for SSDs is the reliability of the storage elements over the life of the SSD. Over time, relatively high gate voltages applied to the storage elements during program and erase (P/E) cycles in the SSD may cause cumulative permanent changes to the storage element characteristics. Charge may become trapped in the gate oxide of the storage elements through stress-induced leakage current (SILC). As the charge accumulates, the effect of programming or erasing a storage element becomes less reliable and the overall endurance of the storage element decreases. Additionally, an increasing number of P/E cycles experienced by a storage element decreases the storage element's data retention capacity, as high voltage stress causes charge to be lost from the storage element's floating gate, resulting in increased Bit Error Rate (BER) of the memory storage device.
SSDs manage errors by retiring blocks when either a program or an erase operation of the block fails. Once a read or erase operation in a block fails, all readable data in the block is moved to storage locations in good blocks and the block is retired. This is typically done by marking the block as a “bad block” by indicating the address of the block in a bad block table. One problem with this approach is that a block can be good and then become uncorrectable before the following operation. For example, this could occur during retention.
Accordingly, what is needed in the art is a system and method that will decrease the BER of individual NAND-based flash memory chips and the overall BER of the data storage device. Also, a method and apparatus is needed that will reduce the number of failures during retention and that will reduce the number of uncorrectable bit errors.